In high-speed communications equipment, e.g., optical transceivers or high-speed input-output (I/O) interface circuits, current-mode logic (“CML”) buffers are frequently employed to drive off-chip resistive loads. CML buffers generally are able to operate from relatively low power supplies and achieve very fast switching high speeds, e.g., greater than a gigahertz or several tens of gigahertz. Further, because CML buffers use differential signaling, they are relatively insensitive to common-mode noise.
A conventional CML buffer circuit is shown in FIG. 1. CML buffer 100 includes two local (on-chip) 50-ohm resistors R1 and R2, two input transistors Q1 and Q2, and a “tail current” transistor Q3. As shown in FIG. 1, resistors R1 and R2 are connected between a supply voltage VDDO and the current-supply (or “drain”) terminals of transistors Q1 and Q2, respectively. The current-sink (or “source”) terminals of transistors Q1 and Q2 are connected together at node A to the current-supply terminal of transistor Q3. Finally, the current-sink terminal of transistor Q3 is connected to ground.
Conventionally, CML buffer 100 has a differential input signal, formed from two single-ended signals DATA and DATA_B applied respectively to the control terminal (“gate”) of transistors Q1 and Q2. In accordance with the differential signaling approach, input signals DATA and DATA_B have opposite polarities. CML buffer 100 further has two outputs OUT_B and OUT, which similarly form a differential signal. The outputs OUT_B and OUT of the CML buffer are further connected to off-chip resistors R3 and R4, that represent the termination impedance of a chip that receives the differential output signal.
In operation, a constant bias current IB is introduced to the CML buffer by transistor Q3. Current IB is predetermined and set by the bias level of the IB current source transistor. As is well-known in the art, current IB is provided by transistor Q3 via a current mirror connection.
By means of input signals DATA and DATA_B, current IB is steered either to the left branch formed by resistor R1 and transistor Q1 or to the right branch formed by resistor R2 and transistor Q2. For example, if input signal DATA is a logical value “one,” or “high,” while input signal DATA_B is a logical value “zero,” or “low,” the current through transistor Q1 will increase and the current through transistor Q2 will decrease (though not so much as to put transistor Q1 or Q2 in a cut-off or active state). Accordingly, because more current flows through resistor R1, a voltage drop across resistor R1 will develop, and the output OUT_B will take on a “low” value. At the same time, because less current flows through resistor R2, the voltage drop across resistor R2 will decrease, and output OUT will take on a “high” value. Alternatively, if input signal DATA is a logical “zero” signal, then current is steered through the right branch, and output OUT_B will take on a “high” value while output OUT takes on a “low” value.
In this conventional CML buffer, and with reference to FIG. 2, the voltage swing of each output signal (i.e., at outputs OUT and OUT_B) is from a maximum output voltage VOH (210 in FIG. 2) of approximately the supply voltage VDDO (also 210 in FIG. 2), down to a minimum output voltage VOL (230 in FIG. 2) obtained by subtracting the voltage drop across resistor R2 or R4 from VDDO. The average value of the output signal (e.g., at output OUT) represents the “common-mode voltage” VCM of the output signal (220 in FIG. 2). Common-mode voltage VCM may be approximated by assuming equal current flow through the left branch and the right branch, with the following resultant circuit equation:VCM=VDDO−(R2+R4)/2*IB/2,where VCM is the common-mode voltage, VDDO is the supply voltage, R2 is the on-chip resistance, R4 is the off-chip resistance, and IB is the tail current. For example, for R1=R2=R3=R4=50 ohms, VDDO=1.2 ohms and IB=20 mA, the resulting common-mode voltage VCM would be 0.95 volts, which is relatively high (i.e., close to the supply voltage VDDO). In addition, the peak-to-peak voltage Vpk of the output signal (250 in FIG. 2) is the voltage at the highest output level VOH minus the voltage at the lowest output level VOL. Maximum output voltage VOH is approximately the supply voltage VDDO (i.e., about 1.2 volts when transistor Q2 is “off”). Minimum output voltage VOL (when transistor Q2 is “on”) may be determined as follows:VOL=VDDO−(R2*R4)/(R2+R4)*IB where VOL is the voltage of the output signal OUT at its lowest output level, VDDO is the supply voltage, R2 and R4 are the on-chip and off-chip load resistances, respectively, and IB is the tail current. For the values used above, where R2=R4=50 ohms, and IB=20 mA, the resulting minimum output voltage VOL would be 0.7 V. Thus, the peak-to-peak voltage Vpk would be VOH−VOL, or 1.2V−0.7 V=0.5 volts.
A significant problem arises, however, when a CML buffer is connected to a receiver through a DC blocking capacitor (known as “AC coupling mode”). Such a connection is shown in FIG. 3. DC blocking capacitors C1 and C2 pass the AC part of the output signals at outputs OUT_B and OUT, but block the DC part of the signal. When the outputs OUT_B and OUT are AC coupled, the dynamic (AC) part of the signal “sees” the local 50-ohm resistance of resistor R1 or resistor R2 in parallel with the remote 50-ohm impedance of resistors R3 or R4, resulting in an equivalent AC impedance of 25 ohms for each output. Meanwhile, the DC part of the signal (i.e., the DC common-mode voltage) “sees” only the 50-ohm local impedance of resistor R1 or resistor R2. The relatively high 50-ohm impedance seen by the DC part gives rise to a relatively high voltage drop (or “IR” drop) of the common-mode voltage. Indeed, the DC impedance (50 ohms) is twice that of the AC equivalent impedance (25 ohms).
The common-mode voltage, maximum output level, and minimum output level for an AC-coupled CML buffer may be calculated in a similar manner as above. The common-mode voltage is:VCM=VDDO−R2*IB/2=1.2 V*50 ohms*20 mA /2=0.7 V.Assuming that C1 and C2 are large, the peak-to-peak voltage from an AC standpoint is about the same as above, or 0.5 V. Because the AC voltage is superimposed on the lower DC common-mode voltage of 0.7 V, the maximum output voltage VOH here is 0.95 V and the minimum output voltage VOL is 0.45 V. The various voltages for the AC-coupled case are depicted graphically in FIG. 4. It may be seen from FIG. 4 that the AC differential signals at outputs OUT_B and OUT swing about the common-mode voltage VCM (430 in FIG. 4), up to VOH (420 in FIG. 4) and down to VOL (440 in FIG. 4) relative to ground 450.
It is clear from the foregoing that in the AC-coupled CML buffer, the DC common-mode output signal is significantly lower than in the DC-coupled case, while the AC output signal remains the same. The large downward shift in the common-mode voltage VCM negatively impacts the AC output signal, however, by limiting the headroom or voltage swing that is available. As a result, at low power supply voltages (for example, 1.2 volts or less), “clipping” or distortion of the output signal may occur. More particularly, in a CML buffer it is preferable to operate both the input transistors Q1 and Q2 and the tail-current transistor Q3 in saturation mode. The very low level of the minimum output voltage VOL (0.45 V), however, causes these transistors to tend to operate in active or cut-off mode, causing distortion or clipping.
One possible solution to the distortion problem caused by the lower common-mode voltage in AC-coupled CML devices is to increase the width to length ratio of transistors Q1, Q2 and Q3, so that they are kept in saturation mode even for relatively low common-mode voltages. In practice, however, the benefit of a high W/L ratio must be balanced against the parasitic capacitance of the devices, which increases as the W/L ratio increases and which tends to reduce the switching frequency of the devices. Thus, it would be desirable to provide an AC-coupled CML buffer that does not suffer from the low-common-mode voltage problem described above and that may operate at high frequencies.